Design Of Low Power Consumption And Variable Precision General FFT Processor Based On FPGA

Since the mid-term of twentieth century, the basic and key theory of digital signal processing--FFT, has become the major subject of many researchers. The FFT processor has found wide applications in such fields as communication, radar, medical engineering. Many of them require that the FFT processors have more points, better real-time processing ability, and flexibility and low power consumption. This research with the general FFT processor based on FPGA shows very strong application value, proving its low power consumption, high precision in addition to multiple point number setting.Firstly, the radix-2and the radix-4algorithms--the FFT algorithm easy to be realized based on hardware, were analyzed, with the latter one compared with the others and finally selected as the algorithm implementation. According to power consumption theory, the lowest power structure--single butterfly, was chosen as the system hardware structure. In the implementation of butterfly computation unit, a new variable precision arithmetic unit was put forward, to improve the butterfly unit data processing range and accuracy; combination optimization algorithm radix-4, only a complex multiplier was required in the butterfly, allowing the system to further reduce the hardware resource consumption; in butterfly unit design process, data-enabled and gated clock were implanted, to reduce the power consumption. Ping-pong structure with reading and writing in the pipeline mode, was chosen as the storage structure, so that the data can be read and calculated uninterrupted. An address generator was designed to provide three addresses and simplify the system controller.This design is based on the Cyclone Ⅱ EP2C35F673C6to achieve. The configured-FFT processor system is verificated by the Matlab simulation algorithm and Powerplay, power analysis software internal integrated in Quartus Ⅱ.Accoding to the vertificated result,9.1μs is required to complete256point FFT calculation.Compared to the current best speed, the speed is improved by29%; The system power consumption was0.65mW/MHz; Thus, we can conculed that the system meet the requirments of high speed with low power consumption.