Resarch And Implementation Of GPON Dynamic Bandwidth Allocation Algorithm

With the rapid development of Internet technology, the demand of bandwidth isgrowing in the past decade. Access network technology innovation is so imperative forthe direct user-oriented access network becomes the barrier of bandwidth improvementin the current network architecture. Therefore, fiber-to-the-home (FTTH) technologycame into being in this historical environment. With its characteristic of high efficiency,easy maintenance, low cost, etc, Gigabit Passive Optical Network (GPON) technologybecomes the best choice of FTTH solutions.First, GPON’s development, technical advantages and TC layer protocol isintroduced and discussed in this paper based on ITU-T G.984Recommendation. On thisbasis, leads to the dynamic bandwidth allocation (DBA) which is the key technology ofGPON, followed by the description of DBA mathematical model. After the introduction,existing research that focus on DBA is discussed.There are many difficulties to implement existing studies that are based onsimulation model, such as computational complexity, FEC encoding, ranging window,frame overhead, and so on, which have a great impact on DBA. Based on thesedifficulties, this paper proposes innovative mechanisms that include multi/single frameT-CONT, FEC overhead recovery, computing and sending separation, windowcompensation, etc. A new DBA algorithm which is realizable and efficient is welldesigned by combining existing studies with new mechanisms.Subsequently, GPON DBA’s reference model is built according to the algorithmdesign, which can provide guidance to chip design on one side and performance resultsthrough this simulation platform on the other side. Then run simulation that’s based onreal network scenarios to get performance of DBA through test cases of the model. Thesimulation data verify that the new algorithm has increased bandwidth utilization andreduced packet delay which influence users’ feelings a lot.Then, implement DBA algorithm based on the reference model. In the architectureof the design, DBA is divided into software part and hardware part in the architecture ofthe design. A built-in processor which can complete DBA calculation function in the chip is responsible for software part, while the extra logic module which can completethe BWmap conversion is responsible for hardware part. The software part’s processflow, algorithm theory, formula derivation is first described, followed by theintroduction of assembly code that completes algorithm process. Thereafter, descriptionof the algorithm’s software and hardware parts is arranged at the last of this paper.Finally, the measured data that’s obtained through performance test in real sceneshow that the packet delay is less than1.5ms and Ethernet throughput is more than1Gbps, which meet the carrier’s target of access network products.