The Design And Verificationof IEEE1394Physical Layer Core

With the rapid development of information technology, people have put forward ahigher requirement for the transmission speed of the computer peripherals. And it hasimerged many interfaces, such as USB, IEEE1394, FiberChannel, SSA and Ultra SCSI.As a high-speed serial bus standard, the IEEE1394has a great advantage intransmission speed and reliability. Not only does it support hot-swappable, but also hastwo communication modes named isochronous transmission and asynchronoustransmission. It is widely used in the aerospace, digital video cameras, high-speedexternal hard drives, printers and other equipment.The IP core studied by this article is a module of IEEE1394chip. It takes charge oftransmitting data from the link layer to the bus and receiving data from the bus. The IPcore complies with the protocol of IEEE1394a. It accomplishes the basic function ofphysical layer. The maximum speed of transmission is up to400Mbps. It can betapeouted alone or be made into an SOC product with other layer. It has a great valuefor studying the chip of IEEE1394.First, this article analyzes the basic content of the IEEE1394protocol. And itfocuses on the mechanism of arbitration and the theory of communication. Second, weput forward a solution of system-level based on the function of physical layer. And wedesign all submodules. Meanwhile, we develop the external interfaces and the internalstate machines. We use an idea of top-down designing for the whole process. In order toensure correctness and reliability of this design, we finally build up the testbench onsystem-level and develop a detailed plan of simulation. And we verify the function ofthis design with the tool of Modelsim6.5. The results show that the function and timingof this design meet the requirements of protocol.