Hierarchical Structure Of The Cluster Virtual Bus On-chip Interconnect Network Design And Research

The rapid development of semiconductor technology met the bottleneck problem to improve the performance of the high power consumption, performance limits and interconnection delay caused by on chip integration of more large-scale hardware resources and chip design. NoC (Network on chip) design architecture, making the design based on the calculation to on the communication, achieved scalable communication architecture. NoC (Network on chip) as a new on-chip network communication, overcame the shortcomings of the traditional bus system, significantly improved the performance of the system. It is considered to be the inevitable direction of future multi-core technology development.In order to more effectively organizing and using the on-chip multi-core processor, the thesis studied classical network communication architecture according to the existing network on chip, introduced mature high performance cluster system into chip multi-core processor architecture. According to the characteristics of cluster system, this article studied the communication features and communication requirements for cluster systems, put forwards the classification of the virtual bus interconnection network architecture based on cluster system, according to the dynamic request to reconfigurate of virtual bus based on the existing Network on chip, it supported multi-core data communications providing service of low delay of unicast and high performance of multicast/broadcast.This article use EDA tools and Verilog HDL language of Altera company to design communication node, network interface and cache structure of simulation system, using the Quartus Ⅱ8.0to integration, wiring and simulation to complete the basic data reading and writing transmission tests, can work normally under50MHz clock frequency with the goal of EP2C35F672C6chip of Altera company to download.The testing results show that the system can meet the basic requirements of heterogeneous multi-core processing unit for data access. The routing complexity and^data channel utilization rate had certain complementary compared with the traditional NoC packet forwarding mechanism. The parallel bus interconnection structure was superior to the traditional parallel data access. The thesis provided support for further optimize design and applied research. I believe that through the similar research and exploration to this article, we can also find more optimized system interconnection architecture design solutions suitable for the target system with more and more excellent on-chip network topology structure and communication methods.