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Bun-Time Feature Based Energy Saving Study For GPGPU

Posted on:2014-03-16Degree:MasterType:Thesis
Country:ChinaCandidate:J M LeFull Text:PDF
GTID:2268330395489214Subject:Computer architecture
Abstract/Summary:PDF Full Text Request
As GPGPU is widely used in general purpose computing field, the applications put forward higher demand of GPGPU’s computing ability. In order to meet the need of the applications, more and more processing units are integrated in GPGPU and the working frequency of the processor unceasingly increases. Although the computing ability of GPGPU has been improved, the energy consumption of GPGPU has dramatically augmented. The increasingly serious energy problem has become the main obstacle which restricts GPGPU to be applied in more fields.For program with more computing instructions, the advantages of GPGPU’s multithreading can be reflected. For program with more memory access instructions, SIMD pipelines frequently stall for memory access latency, so the computing ability of GPGPU is underutilized. When many pipelines pause, the power consumption can be reduced without the serious sacrifice of the program performance by lowering the core frequency to match the memory access rate.This paper observes that there is considerable difference in the program performance while GPGPU is running. We divide the program instructions into memory access instructions and computing instructions, and analyze the effect of the two kinds of instructions on program performance. While the program is running, the pipeline may stall for memory access latency. In order to describe the pipeline stall because of memory access latency, warp issue rate is proposed as the unified index, which is the average number of warps issued by per SM in per clock cycle. This index can assess the performance of GPGPU programs on instruction level.According to the relationship between power and frequency, and based on the run-time feature of programs, this paper proposes that scaling the frequency of GPGPU can achieve the tradeoff between performance and power consumption. When the warp issue rate is high, the program runs at a higher frequency to ensure the performance. When the warp issue rate is low, the program runs at a lower frequency to reduce the power consumption. A Static Voltage/Frequency Scaling (SVS) strategy and a Dynamic Voltage/Frequency Scaling (DVS) strategy are proposed, the former decides the appropriate frequency through offline analysis of programs, and the latter adjusts the frequency according to the run-time characteristics of programs online. At the same time, we analyze the advantages and disadvantages of the two strategies and point out their suitable application scenarios.The processor power simulator Wattch can compute the power of components in the processor, which is mainly used to simulate the CPU power. This paper studies and modifies Wattch, and combines it with a cycle accurate GPGPU simulator GPGPU-Sim to simulate the GPGPU power. We confirm its accuracy by running several benchmarks and comparing their power with that on the real GPGPU.In order to test the performance of the two voltage/frequency scaling strategies put forward in this paper, we implement the two strategies in the platform combining Wattch and GPGPU-Sim. Six typical benchmarks are selected and tested, and their results are compared with the baseline. The results show that SVS saves energy by19.7%with13.1%performance sacrifice on average, and DVS saves energy by18%with13.4%performance sacrifice on average. For some application, both of the two voltage/frequency scaling strategies can save up to about40%of the energy consumption, but only lose about8%of the program performance.Therefore, this thesis focuses on energy consumption of GPGPU, and presents two voltage/frequency scaling strategies. Both of them can obtain good energy saving effect without the serious decline of the program performance.
Keywords/Search Tags:GPGPU, DVS, memory access latency, pipeline stall, energy saving
PDF Full Text Request
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