| A last-level cache miss would cause the processor’s pipeline stalled for considerable time waiting data from DRAM,which severely degrades the system performance.Hence,estimating DRAM access latency is an important part of system performance evaluation.Researches on analytical models of DRAM access latency fall into two main categories,one that analyzes the trace of requests or DRAM commands,and the other that uses queuing theory to explain the process of DRAM access.The former tends to ignore the impact of request interarrival on the queuing delay,while the latter requires that the request interarrivals are exponentially distributed,which lead to significant error in single-core scenarios.Besides,these models also share some common problems,such as ignoring refresh,write mode,etc.The major contributions of this thesis conclude as follows:(1)dividing the DRAM access latency into queuing latency and service latency,and analyzing the influencing factors of each part;(2)revision of the previous model of our research group,in which the model proposed by Sun Fengying is modified with refresh and write mode considered and the row buffer hit ratio equation of the model proposed by Ji Kecheng is corrected;(3)proposal of an trace-driven DRAM access latency model,which takes LLC misses/write-backs trace as input to calculate the total latency of each access request.This model makes up for the deficiency of the previous analytical models.In this thesis,23 SPEC CPU 2006 benchmark are evaluated to validate the modified prior model and the trace-driven model.Comparing with Ramulator,a cycle-accurate simulator,the mean absolute percentage error reduction of DRAM service latency estimation is 77.1% for the revised version of Sun Fengying’s model and 15.8% for the revised version of Ji Kecheng’s model.The mean absolute percentage error of the total latency estimation of the trace-driven model is less than 0.01% for single core scenario and less than 1% for multi-core scenario.Nevertheless,the evaluation speed of the trace-driven model is 16.7 times faster than Ramulator. |
