Design Of Interface Chip About HF RFID Reader

RFID(Radio Frequency Identification) technology is un-touchable autoidentification technology.To complete bi-directional communication, RFID systemidentifies object and acquires data by RF signal. An integrated RFID sysytem iscomposed of top-level u-controller, reader, antenna and tag. Reader plays animportant role in this system and is a bridge of the top-level cotroller and the tag. Thispaper presents the design and implementation of interface contrller for HF RFIDreader chip.Firstly, The paper analyses system theory of the auto identificationtechnology,explains the role and status of reader in the RFID system, and thearchiteture of reader system.And then, understand the function about interface chipand define the design of the digital logic. The main content about this paper is to solvehow the digital logic communicates with analog circuit and external u-controller andhow to buffer the data.The paper describes the design of SPI（Serial Peripheral Interface）intherface andknow the advantage of serial bus such as operate simply, high rate, flexible logicextend and so on. So, the external u-controller communicates the chip by SPI. Itenhances the function of logic lay about SPI, comes up with concept of chip bus inorder to oganize the register and operate the chip.The circuit of the design is appliedin the system of smart card. So, according to the protocol of the ISO/IEC14443,.thedesign of Miller encoding circuit, Manchester bit decoding circuit and BPSK（BinaryPhase Shift Keying）decoding are described on the base of demodulation. Meanwhile,It is necessary to consider the stability of communication. As a bridge between smartcard and external u-controller, the design need to buffer the data which are exchangedbetween them.Compare with tradition design, the paper makes a method that bufferthe data uses the combination of software and hardware to guarantee accuracycommunication.Meanwhile, the paper comes up with a new architecture about FIFOdesign in order to reduce complexity.To enlarge the flexibility of chip, the design ofinterrupting controller are presented.Finally, the paper provides the simulation result under NC verilog for some keycircuit described with Verilog HDL such as SPI interface, FIFO bumper, state machine,encoding and decoding circuit. And then It provides the pro-type verification result bysmart card under platform which is composed with Xilinx FPGA, chip of MSP430and RF circuit. After that, the chip is tapped out at TSMC. The packaged chip istesting and reaches the prospective require.