Failure Analysis And Modelling Of Power MOS

This thesis firstly introduces the Power MOS marked demand, and thedevelopment. Then introduces the work mode, and the process flow, step by stepshows the process information and function, from epitaxial wafer to front end finish.This thesis’s work is, focus on Power MOS major4parameters: VGS, BVDSS,RDSON, IGSS failure mode analysis, one by one do theoretical analysis and failureanalysis cut. Then base on the failure mode analysis result, fix the final root cause.And give a proposal for improvement through process tuning. For VGS, study theabnormal of wafer edge which caused by poly etch pool uniformity and trench tooclose to CT, and give solution by optimize the poly etch rate uniformity and reducethe trench CD. For BVDSS, find failure is caused by parasitic BJT and MOS, thengive solution by optimize the poly etch rate uniformity and eliminate the CT holemissing to eliminate parasitic BJT, by increase FOX thickness to eliminate parasiticMOS, and then BVDSS fail issue is solved. For RDSON failure, study the edgefailure mode and overall failure mode, and give solution by reduce trench and CT CD,optimize trench to CT overlay to reduce channel resistance, and also by add thermalSiO2to reduce extension resistance. For IGSS failure problem, the solution is tooptimize etch rate uniformity to remove poly and metal residue.At the last, summarize each parameter failure mode, improvement action. Andshow a good effect to research and manufacture. This thesis’s significance give amethod for Power MOS inline issue check and yield improve.