Study On Failure Model Of SiC MOSFET Devices Under Avalanche Condition And Its Reliability Improvement

Silicon carbide(SiC)metallic oxide semiconductor field effect transistor(MOSFET)tends to be widely used in power electronic devices with high frequency and high power density performance.However,SiC MOSFET has inherent ultra-high switching speed,leading to be driven into avalanche condition due to over voltage induced by coupling with inductor,and the gate-oxide layer of devices suffers very high electric field during avalanche period.Moreover,the gate-oxide layer in SiC MOSFET is relatively weak,the SiC MOSFET devices thus are confronted with chanllenges of avalanche failure.Focusing on failure mechanism and its improvement method of SiC MOSFET under avalanche stress,this thesis carries out studies on modeling of cell chip and thermal network with temperature dependence,failure mechanism under different avalanche shock mode and improvement method for repetitive avalanche ability.The main research contents of this thesis include:(1)Aiming at the problem that the electrothermal stress in SiC MOSFET devices is difficult to analysis directly under avalanche condition due to the complicated inner electothemal coupling of devices,the cell level chip model and temperature dependant thermal network are built.First,based on widely used commercial SiC MOSFET devices,principle parameters and geometery structure are obtained by scanning electron microscope analysis.And a numerical simulation cell model which can reflect the avalanche process of SiC MOSFET is built.Then,considering temperature dependant property of material thermal characterisitics,the transient thermal network of chip is built.Finally,the proposed model is validated by experimental results,and then electrothermal distruibution law of SiC MOSFET during avalanche period is revealed.(2)Aiming at the problem that the unclear failure mechanism of SiC MOSFET under avalanche condition,the failure evolution process under different avalanche shock mode is studied.First,based on single avalanche pulse experiment,the failure simulation model of SiC MOSFET is built,and then the electrothermal distribution in SiC MOSFET during failure process is obtained.Next,based on repetitive avalanche pulse experiment,the failure simulation model of SiC MOSFET under repetitive avalanche is built,and degradation parameters is analyzed,then electric stress distribution in SiC MOSFET during failure process is obtained.Finally,by means of results comparison between simulation and experimental,the failure mechanism of SiC MOSFETs under different avalanche mode is verified.(3)Aiming at the problem that low reliability of SiC MOSFET under repetitive avalanche induced by poor gate-oxide quality,the optimization method for chip structure design is proposed to increase cycling lifetime under repetitive avalanche condition.First,with the purpose of improving lifetime of repetitive avalanche,a cell optimized and improved structure of gate-oxide layer and JFET region is designed based on the mechanism of repetitive avalanche failure.Second,based on the analysis method of failure physics,a repetitive avalanche lifetime model considering the impact ionization rate and interface electric field strength is established on the basis of hot-carrier-injection-oxide-layer degradation model.Finally,the TCAD simulation is used to analyze the stress and lifetime of the improved design structure under avalanche condition to verify the effectiveness of the proposed structural optimization.The research results of this thesis provide technical support for the failure mechanism analysis and reliability testing and evaluation of SiC MOSFET devices under avalanche condition,and also are beneficial to laying a solid foundation for the reliability design of SiC MOSFET devices.