Cross-correlation Image Matching Coprocessor Logic Design And Implementation

Image matching has become an important technology in the field of moderninformation processing. It is widely used in military and civilian fields. As an classicimage matching algorithm based on gray scale, Zero-Mean NormalizedCross-Correlation (ZNCC) has the advantages such as ease-of-implementation, highmatching probability, high signal to noise ratio and so on. But at the same time,ZNCC needs to process a large amount of data, and the high complexity of algorithmleads to a long computation time. Thus, its application in real-time system is limited.In order to meet the real-time requirement of image processing system, this thesisproposes a FPGA-based ZNCC image matching computing architecture, andimplements it as a ZNCC image matching IP core. By optimizing the architecture,algorithms compute cycles, the maximum operating frequency of the circuit andcalculation accuracy are significantly improved than the existing architectures. Toimprove the applicability of the system, this architecture takes into account bothcaching reference image in internal memory and external memory, to meet the needsof processing different resolution reference images. And the resolution of bothreference image and real-time image can be configured. This architecture also usesSobel edge enhancement operator for image preprocessing to suppress noise, sharpenthe correlation peak. Simulation is done in Quartus II12.0and ModelSim10.0. And aboard level verification is done in Stratix IV FPGA. Experimental results show thatcomparing to the existing design proposed in other papers, the IP core reduces thealgorithm computing cycle by about6%, maximum frequency of the circuit isincreased from100MHz to more than200MHz, computing accuracy is increased from106to108. When using the IP core to match320×256reference image and64×64real-time image, it can be done within16.12ms, which can meet the requirements.Then, this thesis analyzes the Link Port and Serial RapidIO high-speed interface.Design and implement these two kinds of interfaces in FPGA, while use logicsimulation tools, on-chip logic analyzer to verify the logic functions. And atransmission test is done to check the transmission correctness.Finally, this thesis presents a cross-correlation image matching coprocessorarchitecture, which combines the image correlation matching IP core and high-speedinterface logic. This coprocessor has the advantages such as high data transfer speed,adaptability, flexibility and so on. Based on the existing hardware platform inlaboratory, an ADSP-TS201DSP-based image matching system and a TMS320C6455DSP-based image matching system is separately implemented using this coprocessor.Simulation and test is done to verify the systems.