Study Of Pixel Structure In Small Size Backside Illuminated CMOS Image Sensor

With the development of CMOS process technology and the settlement of somekey technic bottlenecks, CMOS image sensor (CIS) has been widely used in the tabletPCs and smart phones thanks for its series of advantages, such as low-powerconsumption, low-cost, smaller size and randomly reading. It is the use of Back-SideIlluminated (BSI) image sensor that makes CIS achieving widely applications. BSIimage sensor can not only reduce the noise problem of early CMOS sensor, but alsosignificantly improve the ability to detect dark environment which once was one ofthe weaknesses of Front-Side illuminated (FSI) image sensor, making the BSI-CISbecome the mainstream of image sensor. However, with the CMOS process and pixelsize continuous shrink down, BSI has encounterd some new problems. In this paper,some key issues about how to enlarge small pixel’s Full-Well Capacity (FWC) andhow to decrease BSI serious electrical crosstalk are studied respectively.Firstly, in order to improve the small size BSI image sensor’s FWC, the effect ofphotodiode capacitance on improving FWC was studied in this section. And then areformed pinned photodiode structure was proposed. In this new structure, thephoto-generate charges could be not only stored in the traditional N well but also inthe new N well, and a vertical P type region was introduced to help the enlargedcharges achieve fully depletion in the period of reset, this new structure was effectivein enlarging the full well capacity. Secondly, in order to tackle the serious electricalcrosstalk problems in the BSI image sensor, a crosstalk physical model based on BSIpixel was established to study low crosstalk optimization method. Based on theconventional front-side isolation principles, a new structure naming Backside TrenchIsolation (BTI) was proposed. This structure could directly isolate the lateral diffusioncharges so that especially eliminate the BSI pixel’s crosstalk which mainly happenedin the backside of the device layer.The simulation results showed that, the full well capacity has been effectivelyincreased by359.8%which extended from1289e-to6390e-, and simultaneouslyenhanced the quantum efficiency6.3%at520nm. This method to increase full wellcapacity would not sacrifice any level of image lag. Simulation results also show thatthe main source of crosstalk comes from the short and middle wavelength. And when the trench groove depth is above the3/4of total silicon device wafer, the crosstalkcould be effectively reduced from32.73%to8.76%. And especially when the trenchgroove depth is4um, the electrical crosstalk between adjacent pixels could be reducedto only0.2%. After adopting this particular structure, electrical crosstalk can bereduced to0.13%compared with32.73%crosstalk in NONE BTI structure, meaningthe BTI structure can provide a valid basis for the small size pixel back-illuminateddesign.