Process And Device Simulation Of Image Lag Elimination In 4T Active Pixel

CMOS image sensor is an important branch of the semiconductor industry with rapid development. With the continuous progress of CMOS technology, CMOS image sensor can compete with CCD for its ever-increasing performance, and has been widely applied to aspects of social living and industrial production such as digital electronics, medical equipments and industrial monitoring. So, CMOS image sensors have a promising market.Currently, as the mainstream pixel structure of CMOS image sensor, 4T active pixel (also known as pinned photodiode pixel) suppresses the surface dark current and reset noise of pixel, and achieves a real correlated double sampling (CDS), which is important for the design of high-performance and low-noise CMOS image sensors. However, as the supply voltage of CMOS image sensor is about 2.5V~3.3V, which is much lower than CCD, coupled with the trap level and potential variance (pocket or barrier) caused by some non-ideal effects such as non-uniform doping distribution, crystal defects and pollutions in pixel manufacturing process, incomplete charge transfer from the photodiode (PPD) to the floating diffusion (FD) occurs and the residual electrons in the PD region can cause image lag. Therefore, under the condition of current CMOS technology, it is very important of pixel design for eliminating the image lag of CMOS image sensor.In this paper, image lag in 4T CMOS APS has been discussed and optimized from the process point of view with process/device simulation tool ISE-TCAD, also a modeling of signal charge transfer process in the pixel is proposed. We begin with a brief description and analysis of pixel noise in 4T CMOS image sensor, and provide a test method to obtain the pinch-off voltage of 4T pixel based on the potential well structure change in signal transfer process between PPD, TG and FD. The experimental results of pinch-off voltage are important for optimization of pinned photodiode design to improve charge transfer efficiency. Then strategies of reducing image lag are discussed from transfer gate (TG) channel threshold voltage Vt doping adjustment, PPD N-type doping dose/implant tilt adjustment and TG operation voltage adjustment for signal electrons transfer. Finally, an optimum design of charge transfer unit (PPD, TG and FD) in pinned pixel is obtained; also, the optimal process and operational conditions are acquired: minimum image lag can be obtained at pinned photodiode n-type doping dose 7.0e+12 cm-2, implant tilt -2°, transfer gate channel doping dose 3.0e+12 cm-2 and operation voltage 3.4V. The research methods and simulation results in this paper can be a guideline of pixel design which promises to further improve CMOS image sensor performance and broaden their low light level applications.