FPGA-based Fast Image Processing System

In recent years, the image processing technology has been widely used in manyareas. Embedded image processing system has great advatage over personalcomputer image system in mobility and real time characteristics. With rapiddevelopment of embedded processors, the FPGA device enters our life. It hasmillions of gate cells, which is necessary to complish complex system design. Inaddition, FPGA is programmal. Users can “customize” the processors by themselves.In fact, FPGA has became one of the most usually used processors in embeddedimage processing system.The main target of the graduation design is constructing the “softIP+hardIP”image processing system and then doing special image processing task in theconstructed system. The system has there parts: image capturing part, processingpart and output part. For the hardware, we select OV7670as the image input,EP2C8Q32FC8as the FPGA processor and2.8’ TFT as output. What’s more, flashan SDRAM is also necessary for external memory. For system design, we first finishthe image initialization and capture module, TFT switch module in the HDLhardware design layer. Then, with the help of SOPC Builder tool, we can generateour own Nios II system. The Nios II system has fast CPU-Nios II/f, CFI_flashcontroller, SDRAM controller and PIO connected to hardware modules. Union thehardare modules with the Nios II system, we get the FPGA-based image processingsystem.In the experiment part, we first verify the constructed system by displaying theiame captured by cmos camera imediatelly. Then, we chose the algorithm:object-racing of a ball, to find the features of FPGA, by comparing the PC algorisimand FPGA system algorisim. The algorithm is based on the color of the ball, whiledifferent with usual methods, we chose HSV space to deal with the colorinformation in instead of the RGB space. Meanwhile, the coordinate positon of theobject is obtained by contrasting with the prior coordinate position in last frame. Inthe system, the algorism is finished in a “HardIP+SoftIP” module.