Research And Design Of32-bit And Five-stage Pipelined CPU Based On FPGA

At present, computer composed experimental platform of most colleges is pure hardware indomestic. Its internal structure is fixed, so the flexibility is poor.The experimental platform is notconducive to the students’ independent innovation, and it greatly reduces the quality of teaching.FPGA design platform is facile，the32-bit and five-stage pipelined CPU is designed in FPGAplatform in the paper, which can be applied to the experimental courses improves the quality ofteaching.According to the actual need, the combination of theoretical research, in this paper themodel of five-stage pipelined CPU based on the FPGA is proposed, and the32-bit and five-stagepipelined CPU design process is completed in the DE2development platform, the five periodsfunction design is realized, which include IF, ID, EXE, MEM and WB.The pipelineddemonstration system is specially designed in the paper, the reasonable CPU design is verifiedby analyzing the effect of system demonstration.In this paper, the five cycle design of pipelined CPU is completed by VerilogHDL. Throughdesigning PC register and instruction memory, the function is realized in IF stage. In ID stage,the CU and register file are designed, the20instruction decoding function is completed.In EXEstage, ALU is designed, data operation is realized. In MEM stage, the design of data memory iscompleted, and reading and writing operations are realized. The design of multiplexer achievesthe right result written destination register. Pipelined design brings about correlation issues,containing data, control and structure. In the paper, data correlation and control correlation aredetailed researched and processed, the internal front push method and suspended water methodcombining strategy is designed to solve the data correlation issues. And the mean of delayingtranster solves control correlation.The pipelined demonstration system is designed to realize thepipelined demonstration and effect analysis function.Finally, the test program is written in the paper, and the pipelined CPU functions are testedby it in FPGA, the effect of the test program is analyzed, the CPU running is normal, andfunction is completed, then it achieves the desired result.