A table look-up pipelined multiplication-accumulation co-processor for H.264, and, An intellectual property authentication scheme for FPGA through watermarking techniques

A newly developed video standard, H.264/AVC, provides significantly better bit compression ratio and transmission efficiency. To achieve this, much higher computation power is needed. The hybrid CPU/field-programmable gate array (FPGA) chip model contains CPU (DSP) and FPGAs that can be used to reduce design cost and still support significant hardware customization. A H.264 Codec is to be implemented by a high end CPU (RM9000) and two FPGA implemented co-processors. In this thesis, we present a Table Look-Up Pipelined Multiplication-Accumulation Co-processor (MAC) for H.264 Codec, which can be used for a large number of computations in H.264 where one of the multiplicands is a constant. The proposed design is based on the pre-computed tables which generate the partial products and a three-level pipelined architecture. A design simulation with SystemC is conducted to verify functional correctness. A field programmable gate array (FPGA) implementation of MAC with Xilinx FPGA is explored. The result shows that the proposed MAC out performs the conventional multiply-accumulate unit both in size and speed.; This thesis also presents an intellectual property (IP) protection authentication scheme for FPGA with embedded watermark. Watermarking implements IP protection by making untraceable unauthorized reuse as difficult as recreating given pieces of IP from scratch. The authentication process in the proposed scheme is based on creating a watermark by encrypting the signature of the IP user with the unique FPGA board ID, which guarantees that a watermarked FPGA design can only be used on an authorized FPGA board. This could prevent the unauthorized reuses when certain users violate the copyright protection law and resell the watermarked FPGA design with signature to others.