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Hardware Implementation Of JPEG-LS Multi-channel Parallel Decoding Algorithm

Posted on:2011-02-21Degree:MasterType:Thesis
Country:ChinaCandidate:H R WangFull Text:PDF
GTID:2248360305991823Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the advancement of aerospace science and technology, development of space borne remote sensing equipment is moving towards the high-resolution and digital direction. With the increase of resolution, data storage capacity and data transfer bandwidth demand increasingly high, so the quality and speed requirement of data compression preprocessing is rising. In 1997, JPEG (Joint Photographic Experts Group) developed the JPEG-LS standard. The core algorithms include:adaptive prediction, context modeling and Golomb coding, run mode encoding for the flat areas of image. Compare to JPEG, JPEG2000 and other popular image compression algorithm, JPEG-LS has higher compression ratio and lower complexity in the lossless compression field, easy to implement by hardware. FPGA is fast, pins and more easily achieve large-scale system to support parallel and pipelined structure. Therefore, in the communications, data processing, networking, instrumentation, industrial control, military and aerospace and other fields has been widely used.The article presents a realization of JPEG-LS multi-parallel decoding algorithm on FPGA chip, in the overall design, Studied the JPEG-LS standards, and analysed the encoding and decoding algorithms in detail; Implemented JPEG-LS decoding algorithm in FPGA chip with VHDL, and described the implementation process in detail, in view of decoding massive image data in high-speed, In order to achieve the rapid transmission and storage of high-resolution images, single decoder module often can’t meet the demand, so the design implemented parallel decoding with multiple decoding module to improve the decoding speed; The whole system is functional and post simulated in ise7.1i and Modelsim6.3a software environment, according to the result of synthesis and simulation, optimized system algorithm to improve overall performance.The article implemented JPEG-LS multi-parallel decoding algorithm in virtex-4 family XC4VSX55 of Xilinx Company, and tested by a large number of images to verify the validity of the system.
Keywords/Search Tags:JPEG-LS decoding, Multi-parallel, Regular mode, Run mode
PDF Full Text Request
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