The Research Of The Trusted Embedded Platform Based On Software-Hardware Co-Design

With the concept of the Internet of Things proposed and its related technology applied and the development and advancement of technology about Trusted Computing in recent years, Trusted Computing will be the basis for secure communication and information exchange on Internet of Things in the future. Trusted Computing Group (TCG) propose a complete definition set of solutions and standardization of the trusted computing platform to prevent trusted computing platform from encountering threats and attacks of the distrusted entities. TCG defined trusted root, is typically implemented as a trusted platform module (TPM). The core of the Trusted Computing Platform on Embedded system is Trusted Platform Module(TPM) and the core of the TPM is usually efficient implementation of the encryption engine of the encryption algorithm. The most critical core in the TPM is the complex non-symmetrical public key encryption algorithms, such as the RSA public key encryption algorithm, but the computational complexity is particularly high and require specialized hardware such as ASIC implemented coprocessor to meet the performance requirements of the trusted platform. However, the traditional embedded devices often cannot meet such performance requirements of future Internet of Things on embedded trusted computing platform. On the other hand, the embedded trusted computing platform is usually very sensitive to costs, prices, system resource consumption, chip area, and other factors, therefore, the design of TPM module in embedded trusted computing platform is not like that of the traditional computing platforms by increasing hardware resources to implement coprocessor with specialized integral circuit. To address this problem, this paper proposed a method based on hardware and software co-design technology to design and implement an application specific instruction processor to promote the efficiency of the RSA algorithm. The application specific instruction set processor is the processor with the application specific custom instructions to extend the original processor’s instruction set. In such way, the application specific processor can greatly enhance the efficiency of the implementation of the applications using less hardware resources consumption than using an extra coprocessor, while maintaining the flexibility and scalability of the software level. This paper proposed a method for the design and implementation of the application specific instruction processor with extended instructions set.The core of TPM of the Embedded System trusted computing platform is to achieve efficient implementation of the RSA encryption algorithm, however, the computing performance of traditional embedded system usually cannot meet the performance requirements of the embedded trusted computing platform. Therefore, this paper proposed a way to efficient implement the RSA algorithm through an RSA specific instruction processor. AS for the RSA encryption algorithm implemented in the Trusted Module TPM of embedded trusted computing platform, this paper analysis the details of the RSA encryption algorithm and implement it in C programming language, and then using the custom instructions selection method MM-Level algorithm to find the effective customer instructions to optimize and extend the instruction set of the original processor. In this paper, on the basis of a comprehensive analysis of the RSA encryption algorithm, firstly, employ MM-Level instruction selection algorithm to select custom instructions from the core parts of the RSA encryption algorithm. Secondly, using the factors of embedded trusted computing platform, such as the resources of the system, area, speed, translate it to an integer linear programming problem (ILP). Finally, the processor model will eventually be implemented in FPGA platforms. In this paper, the realization of the RSA application specific instruction set processor employs the popular method in the international electronic system-level ESL (Electronic System Level) design domain and use a dedicated instruction set architecture language LISA (Language for Instruction Set Architecture) language of the RSA algorithm. The ASIP processor mode with the optimized extended custom instruction set of the RSA algorithm, will eventually generate a processor model on the FPGA.