The Realization And Improvement Of Chaotic Data Encryption Standard Based On FPGA

DES (Data Encryption Standard) encryption algorithm since the1970s has experienced a long-term test. Prove the security of the DES algorithm can completely meet the safety requirements in the most of the practical application. DES algorithm itself only requires the use of logical operations in the encryption/decryption process and the key generation process and table checking operation, the mathematical calculation is not complicated, so the hardware implementation of the scheme can optimize system performance also enhance the plus decryption speed.Software implementation of DES encryption algorithm’s encryption speed is low and the key may expose during encryption/decryption. Hardware implementation can slove these problems. FPGA can achieve large-scale circuits designs and flexible programming, it’s design and development cycle is short, owns advanced develop tools costs less. Developed stable product quality can also be real-time online testing. In this paper, FPGA-based DES encryption algorithm is studied and realized.DES encryption algorithm exists short keys and the key space is insufficient. As computer hardware technology and advances in cryptanalysis, DES encryption algorithm subject to greater security threat. The DES algorithm security is mainly depended on key security protection, with the development of Chaos,"Chaos Password" research attracts more people’s attention. This paper realized a DES key generation algorithm based on chaotic system combining the characteristics of chaotic systems with the characteristics of the DES encryption algorithm.The main work includes:(1) Research on the DES algorithm is carried out and made more understanding of the basic principles of the DES algorithm。Combined with study of chaos and encryption in the chaotic system, the research has lain a great foundation of the DES algorithm system based on FPGA and the DES algorithm based on Logistic chaotic model. (2) The DES algorithm system has been realized on Actel’s ProASlC3/E A3P1000device. This has made a well preparation for the realization of chaotic DES algorithm system on hardwares and the performance analysis. In the implementation process, through the performance and the amount of system resources usage into account, has developed a3-pipeline structure password generation module. S-box is critically important to the DES algorithm or hardware performance of the algorithm, this paper implements a ROM implementation of the S-box designed to enhance the performance of the hardware implementation.(3) Proposed a algorithm which DES keys are generated by a one-dimensional model of chaotic Logistic. The detailed study of Logistic chaotic model is carried out. And the simulation results verify the good chaotic performance of the model. Proved the feasibility of the chaotic algorithm by simulation on Matlab R2012b.The experimental results were analyzed qualitatively and different example are contrasted. The design proved beneficial for the improvement of the DES algorithm.