Research And Application Of Ti’s C66Multicore Digital Signal Processor Technologies

This thesis comes from an LTE terminal test set development project, which is undertaken by Beijing University of Posts and Telecommunications and a company. The author is mainly responsible for designing and implementing the underlying interface drivers for TI’s C66series DSPs on the baseband board, including boot methods and high-speed interface communications. In the first part, SPI boot, PCIe boot and multicore boot function are implemented, while in the second part,3kinds of serial high-speed interfaces AIF2, HyperLink and PCIe are researched and designed for normal communications.At the beginning of this thesis, the architecture and new characteristics of LTE communication system are briefly reviewed, and then the background and main contents of the thesis are presented.The second chapter outlines the architecture of LTE test set, and then highlights the baseband board design and C66x DSP, showing the hardware platform of the thesis.The third chapter mainly describes the boot methods design part, according to the boot demands of the board and the boot principles of C66x DSP, the thesis designs and finishs DSP’s SPI boot, PCIe boot and multicore boot function.The next is the high-speed interface design part, covering a total of three chapters. The forth chapter first outlines the3high-speed serial interfaces on the baseband board, and then focuses on studying AIF2interface and its transport protocol, synchronization mechniasm, and finally finishes the AIF2communication between DSP and FPGA. The fifth chapter focuses on the research of HyperLink interface and its transport protocol, and then implements the HyperLink communication between the two DSPs. The sixth chapter focuses on the resarch of PCIe interface and its transport protocol, and then completes the PCIe communication between PC and the two DSPs on the board.The last chapter makes a brief summarization of the whole thesis.As an important part of the LTE terminal test set, the baseband board’s core processor is DSP. This thesis designs and implements different boot methods and high-speed interface communications for the C66x DSPs, so that they can be successfully used on the baseband board, which has great significance on the development of the LTE terminal test set.