Design Of Low-Power10-bit Successive Approximation Register ADC For The Monolithic Integrated Sensors

With the rapid development of VLSI technology and MEMS technology, making the monolithic integrated sensor technology has become the main direction of the sensor research. Based on the monolithic integration of sensors not focusing on its internal A/D converter’s speed and resolution, low power consumption should become a key consideration when the former two performances meet the requirements. In view of the successive approximation ADC is the best structure in high-resolution, low-power ADC design. This paper on the basis of the traditional SAR ADC adjusts and improves each sub-module, so as to achieve low power consumption requirements.This thesis based on the CSMC0.5μm DPTM CMOS technology, achieves a10-bit2MS/s SAR ADC. It contains four sub-modules, such as sample-and-hold circuit, the DAC module, comparators, and digital control logic. The sample-and-hold circuit uses the bootstrapped switch to improve the linearity of the switch and to reduce the distortion, to achieve accurate sampling. Adjust switching procedure of its capacitor array, to reduce the power dissipation of the DAC. Use a dynamic comparator with current source, because its current is changing with the working state, which can reduce the power consumption of the comparator. On the Cadence workstation, simulate and verify the function of each sub-circuit and the whole circuit by Spectre and Matlab, and adjust its parameters to achieve requirement. Finally, to finish its layout on the Virtuoso software, design rules check and electrical rules check on the Dracula software. Achieved580kS/s sampling rate and frequency of13kHz signal input, the SNR of the circuit is59.1806dB, spurious-free dynamic range is79.1101dB. The area of the chip is about1mm2. When supply voltage is5V, power consumption is6.2mW.