Research Of X-band Frequency Synthesizers

With the development of communication and radar technology, the requirement for synthesizer (key technology of whole system)’s performance is becoming higher and higher. High performance and low cost frequency synthesizers are always expected in practical application. Modern frequency synthesizer is mainly based on frequency multiplication, DDS and PLL technology etc. To satisfy the requirement of low cost, low phase noise and minimal stepping, a new type of frequency synthesizer is designed by adopting frequency demultiplier and phase detector controlled by MCU. The frequency demultiplier and phase detector are of Delta-Sigma digital modulation. Meanwhile, another plan is presented to make a vertical comparison about the performance. In this plan, phase-locked loop is excited by DDS in the front end.As modern frequency synthesis technology introduces the theory of Delta-Sigma digital modulation, phase-locked loop can get fractional multiple outputs to obtain the minimum frequency step without changing the reference frequency. Bearing this in mind, first this article discusses the Delta-Sigma theory thoroughly, does model simulation of phase noise and spurious performance in ADS, analyses the influence of loop bandwidth, and discusses the contradiction between optimizing phase noise and improving fractional-N frequency spurious. Then with chips HMC700at the core, according to the requirements of performance, this X band Delta-Sigma frequency synthesizer is equipped with high-order loop circuit, the Keyboard module and Liquid Crystal Module1602. The high-order loop circuit involves HMC506VCO, low-noise operational amplifier AD797as well as a number of low-voltage dropout regulator sources.The commissioning of the circuit mentioned in this paper has been finished. The completed X-band frequency synthesizer has an output power about lOdBm and a tuning range from8GHz to8.22GHz when using10MHz as reference frequency. Its minimum frequency step is1KHz. Phase spurious suppression is greater than50dB. The typical phase noise is better than-89dBc@10KHz when the frequency is an integer multiplier of10MHz. This figure approximately agrees with estimated value according to the manual. Typical phase noise is better than-75dBc@10KHz when the frequency is precise up to1KHz.In this case, the proximal fractional spurs have been submerged in the phase noise and is not visible, which can meet most applications and needs.Then this paper introduces a typical solution of designing frequency, choosing DDS to excite PLL. Then we discuss correlation theories and make a practical design. A parallel comparison is made between the practical design and PLL of Delta-Sigma digital modulation.The results show that, even though the DDS output can get a better phase noise theoretically, but in fact DDS output spectrum phase noise is difficult to do better. For the practical DDS, typical value of the output phase noise is about-96dBc@10KHz and spurious suppression is greater than65dB when the output at250MHz. The poor phase noise lead to relatively poor output of back-end. At the end of chapter, a summary of all of the work is made.