Power Integrity Analysis For Low-power SOC Physical Design

With the development of the Integrated Circuit manufacture process,the integration of chip has become higher,and more and more power is consumed when chip works.The improvement of process and performance make the second-order effects more serious for chip physical design.As the main content of on-die power integrity,IR drop and EM have played an important role in Low-power SOC physical design.This thesis will focus on the research for a Low-power mobile baseband chip X1 which used UMC 28 nm process,and elaborate the power production of SOC and power distribute network model.First,this thesis focus on the issue which On-die power integrity analysis can not be carried out at early floorplan stage,this thesis puts forward an early analysis method:a)By early DC analysis,we complete the discovery and fix for the chip power network at early floorplan stage,and evaluate the quality of power Bumps and switch cells.b)By early AC analysis,we complete to research the generation method for early chip power model.c)By setting up simulation environment for chip-pkg-pcb co-design,we complete to verify the function of generated early chip power model.Than this thesis will summarize the on-die power integrity analysis method at post stage of chip physical design,and evaluate the on-die power integrity of mobile baseband chip X1.The work contains: a)Discovery and fix for the defects for P/G network design at post stage.b)By post power integrity analysis for on-die power network,we complete the work for chip power signoff,ensure the quality for chip physical design.c)In the period of post power integrity analysis,we summarize the post issues of on-die power integrity which is common problems in the chip physical design.Finally,this thesis will research the IR-aware Bump placement and fast IR drop iteration method based on the CPU module of X1 which is based on the Flip-Chip process.By extracting for the block power consumption and resistance path,we establish the equivalent model for on-die P/G network.By using the SA algorithm for fast IR drop iteration,we get the optimum solution for IR-aware Bump placement.The experimental result indicate that the static IR drop of CPU module reduced by 8.91% and the num of instance in the high IR drop range decreased obviously when we optimized the distribution of Bumps using SA algorithm.On-die power integrity became better further.