Million Gate Level FPGA Testing Research Based On ATE

FPGA, Field Programmable Gate Array, it is deeply loved by engineers ofresearching, developing and applying for its abundant interior resources and flexibilityin application. It has been rapidly developed and applied in various fields. Million GatesFPGA chip has been researched and produced by domestic Chinese engineers. Testtechnology has also widely been paid attention and researched. For manufactures ofFPGA chips, ATE, Automatic Test Equipment, should be applied to test the chips in lotsize. J750large scale integrated circuit test system from Teradyne is one of the mostextensively applied test systems domestic China. Thus FPGA test systems researchingbased on J750have good transportability and easy to popularize. They have a certainhigh application value. This paper applies J750for test development platform, appliesmillion gate level FPGA producted by Chengdu Sino Microelectronics Tech.Co.,Ltd asresearch model, research its test method.The main work of this paper is following:Firstly, we study the researching status of FPGA device domestically andinternationally. We analyzed the future development trend of FPGA. And we point outthe research direction and discuss content.Secondly, we particularly analyze the frame and interior construct of the device weresearched in the paper, including Configurable Logic Block (CLB), programmableInput Output Block (IOB), Block selectRAM, Digital Clock Manager (DCM),multiplying unit, interior interconnection and the configuration of the device. Theresearching work in this part defined a direction for the later work in this paper.Thirdly, based on the device construct researching, we analyze the relative faultmodel one by one in this paper. We discuss some theories mainly including exhaustiontest, path scanning test method, built in self test (BIST), boundary scan test method. Wespecifically discuss the fault model and test method for interior interconnection ofFPGA. These theories greatly support the rest discussion of this paper.Finally, applying million gate level FPGA as our target chip, we discuss the specific test method and implementation procedure on J750platform. According to theparticularity of the platform, with the method of conjoining the construct and test thesisof the chip, we bring out some specific practical test method for FPGA to reach milliongates level. Aiming on minimizing the test cost, we carry out high coverage testing forits main construct unit, for it can fulfill the screening test requirement of themanufacturer. It also has good transportability. The researching result of this paperadopts the test program of J750test platform as the pattern of manifestation.For conditional limit, there are still some defects in some construct test for thedevice. It mainly lies in the test for digital clock manager. We only carry out functionaltest for the limit of the test platform. Work still to be done for higher frequency test.Also, we haven’t found a good solution for the fault model of local interconnectionresource to realize simple and effective test. These questions are to be researched in thefuture.