The Design Of DDR SDRAM Controller

With the rapid development of the technology, modern electronic products have diversified, pursuing multi-function, high performance and low-power dissipation in various types of electronic products, and the entire product requires increasingly high on its primary storage devices. DDR SDRAM (Double Data Rate SDRAM, Double Data Rate Synchronous Dynamic Random Access Memory) has been widely applied in these areas of demand for storage devices for its high-speed, large capacity and good compatibility. Requirements for different systems have different trade-offs in the choice of the storage unit. For example, high-performance computers require high frequency and high bandwidth, thus DDRII or DDRIII is a good choice. But for embedded systems, high performance is not the only requirement, its cost and stability must also be considered. Taking all factors into consideration, the DDR SDRAM chip is selected, because DDRIII costs too much and DDRII requires high on circuit board, i.e. the cost of the circuit board which can be applied to DDRII is relatively high. So far in terms of performance, DDRII and DDRIII have some advantages, but for their high cost, people still incline to DDR SDRAM in the choice of embedded memory cell. However, DDR SDRAM and the peripherals need a bridge in between, and DDR SDRAM controller can play this important role. Therefore, the study and design of DDR SDRAM controller has an extremely important value and significance.This paper first introduces the working principle of the DDR SDRAM memory. On this basis, DDR SDRAM instruction and typical operation timing are given; overall module of DDR SDRAM is designed and each module is divided according to the JEDEC industry standard for a given timing requirements, focusing on detailed analysis of key technologies of the DDR SDRAM; in top-down design approach, the controller is implemented by Verilog HDL hardware description language. Last, pre-simulation and follow-up simulation is implemented by simulation tools, and the synthesis and layout route are implemented with Xilinx ISE. Verification shows that the controller design has achieved the desired design requirements and met certain design specifications.In this paper, the design of the controller interface is simple and takes full use of the FPGA clock management resources, making the complexity of the design simplified. Simple operation in the design can also meet the specific DDR SDRAM control and has strong applicability.