Design Of A RS-485Transceiver With Fail-Safe And SR Limitation

Nowadays,in the process of remote control communication,the RS-485protocolhas become the people’s preferred solution.Because the RS-485bus can be designedconcisely,controlled easily and cheap.Due to the widespread application ofRS-485,designing a RS-485communication chip with good performance has a hugeeconomic benefits. RS-485is highly valued in the field of communication, based onthe interface device has a large market, currently in our country and the world’sdominant position in the interface device on the market several manufacturers, suchas Maxim, Texas Instruments. If we can develop more advanced transceiver, not onlyhave enormous economic benefits, as well as a profound social impact.Based on the RS-485communication protocol,using0.5um CMOS technologyand Cadence circuit tool,this paper designs an RS-485tranceiver with high speed,failsafe and slow rate-limiting function.This chip contains receiver and driver.The mainfeatures are as follows:This chip is two-way,half-duplex communication,having strong overloadprotection and power surge protection,as well as input terminal with high as4000Vantistatic ability and receiving terminal with antistatic ability of15000V.This groupof chip has fail-safe circuit that ensures when the input terminal of the transceiver isopen,short or hanging,the output terminal of the transceiver is at the high level of thestate.The limiting point of the driver slow rate is at high frequency,allowingtransmission speed of up to500Kbs,and this chip has very low electromagneticinterference.When the transceiver is with load or with disabled load,the typical valueof supply current consumption is below400uA.Driver limits the short circuitcurrent,and thermal shutdown circuit will set the output terminal of driver to a highresistance state,in order to prevent excessive power loss.Input of the receiver has afail-safe properties that can ensure the output is high logic level.The input impedanceof the transceiver is1/8unit load,which makes the bus support up to256transceivers. In order to achieve more than a few performance innovation, in the followingareas：1. The driver used new slew rate limiting method which can limit the slew rate andensure adequate communication speed at the same time.2. In the receiver there is a hysteresis voltage comparator structure with enoughprecision and speed, and its threshold voltage can be controlled flexibly.3. The structure of overheat protection circuit is simple and sensitive enough togenerate signals that enable the circuit to shutdown when the temperature is hignso that the shutdown system to achieve the purpose of protecting the chip whilereducing static power consumptionThe each part of the circuit was simulated by Cadence Spectre,the result showsthat,both of the function and performance of circuit meet the requirments.