Design And Implementation Of Low Voltage IF Circuit In WSN RF Transceiver Chip

Wireless sensor network(WSN)is a multi-hop self-organizing network system formed by a large number of micro-sensor nodes through wireless communication.Wireless sensor nodes are generally battery-powered,in order to extend the working life of the node,operating voltage should be reduced,and low-voltage low-power wireless sensor network is one of the key technologies.As an important part of the integrated circuit system and WSN,the IF circuit plays a key role in suppressing the interference signal and controlling the signal amplitude in the RF transceiver chip.In order to promote the large-scale application of the wireless sensor network,it is important to study the low-voltage and low-power IF circuit used in WSN.In this paper,TSMC 0.18?m RF CMOS technology is used to design and implement the low voltage IF circuit used in WSN RF transceiver chip.The IF circuit includes two modules:complex filter and limiting amplifier.The complex filter is composed of active complex filter and passive polyphase filter,which solves the contradiction between high mirror rejection and low power consumption of complex filter.For the active complex filter,a pole construction method is proposed to simplify its design flow,and a third-order Butterworth complex filter is constructed through the direct coupling of three single-order complex filters.In order to improve the linearity of the active complex filter and reduce the power consumption,the design of the single-order complex filter utilizes the source feedback and negative resistance techniques.The constant transconductance bias circuit is used to reduce the impact of process corner and temperature variation.The design of limiting amplifier is started from the amplifying unit and the DC offset unit,self-bias load structure is included to improve gain and reduce power.The relationship between the filter parameters and the gain of the DC offset feedback loop is deduced.It is pointed out that the low frequency IF input signal will lead to excessive layout or power consumption.In order to realize the compromise between layout area and power consumption.A limiting amplifier structure with multiple DC offset feedback loops is designed.The chip test results show that the passband of the complex filter covers 0.37-4.1MHz,the input 1 dB compression point is-17.1 dBm,the gain at the IF frequency is 1.04dB,the image rejection is 38.34dB,the adjacent channel rejection is 20.77dB,the channel rejection is 37.49dB with the operating current is 154?A.Limiting amplifier operating frequency covers 1?3MHz,the minimum input signal amplitude of-59dBm,operating current of 759?A.The operating voltage of entire IF circuit is 1V,the operating current does not exceed 1mA.