Based On The On-chip Network Part Of Dynamic Reconfigurable System Research

The digital system designs are often faced with the contradiction between computational efficiency and versatility. To resolve this problem, dynamic partial reconfiguration (DPR) is proposed. With continuous development of the semiconductor process technology, the transistor count in a single chip has grown into billions. The traditional bus structure, as the interconnection of the system, can’t meet the application’s communication efficiency and scalability requirements. In recent years, network on chip (NoC) has been proposed to replace the bus structure, as a highly efficient and scalable communication medium. However, the existing NoC structures, when applying into DPR systems, have ignored the configuration bitstream transmission efficiency. Configuration bitstreams have usually been transmitted through the configuration port of the FPGA chip. In this method, the configuration circuit is connected to all configuration SRAMs throughout the chip, resulting in long interconnections which cause poor bitstream transmission efficiency and make the system lack scalability. To resolve this problem, a new DPR system based on NoC is proposed to take the advantage of NoC to gain high bitstream transmission efficiency and scalability. Works of this thesis are as follows:Firstly, a DPR system chip structure based on NoC is proposed. This structure uses the NoC as the interconnection, and has resource nodes including CPU node, SRAM control node and FPGA IP core node, etc. Each FPGA IP core in this chip is regarded as a reconfigurable region. The DPR system takes the RNI as the interface between the dynamic logic and the static logic instead of bus macro or partition pins which have high dependency on software, thus simplifying the design.Secondly, an NoC structure suitable for DPR systems is proposed and designed. The structure regards the communication data as two types:regular data and configuration bitstreams. It also splits the resource network interface (RNI) into data interface and configuration interface. During the dynamic partial reconfiguration process, the bitstreams are transferred through network, and downloaded into the FPGA IP cores. Thus, bitstream transmittion efficiency is improved. In addition, each IP core has its own configuration interface, making the configuration circuits localized to avoid the long interconnection wires, improving the scalability of the system. Thirdly, the SRAM controller node based on DMA mode is proposed and designed to control the storage and transmission of the configuration bitstreams. Compared to the CPU transmission mode, its transmission efficiency has been improved81times.Simulation test of the NoC shows that it can transmit the regular data, configuration bitstreams and download bitstreams correctly. The synthesis result shows that the maximum frequency of the network is600MHz, and that of the configuration port is150MHz, while that of the internal configuration port of Xilinx FPGA chip is100MHz, indicating the high bitstream transmission efficiency of the NoC. In addition, a prototype system is developed using the Xilinx Virtex4board to conduct FPGA board-level test for the NoC-based DPR system. Experiments show that the prototype system fulfills the tasks of configuring the reconfigurable node from addition to substract, multiplication, or operation and shift operation successfully.