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Design And Implementation Of Router Traffic Management Based On FPGA

Posted on:2016-04-11Degree:MasterType:Thesis
Country:ChinaCandidate:L S LiuFull Text:PDF
GTID:2308330482475211Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
With the rapid development of network technology, transmission of audio, video and other business on IP network grows explosively. The network traffic gradually expands. This puts forwards higher requirement on the performance of the routers. To solve the congestion-control problems becomes the key factor on router performance. Router traffic management system based on the FPGA using the new architecture that combines FPGA and switches together can improve the processing ability of the whole system. FPGA is a programmable, highly scalable and fast data packets processing capacity gate array chip. This new architecture makes it possible to use a combination of hardware and software to solve the internal traffic-control problem of routers.In this paper, traditional best-effort IP network service model as a starting point and the faults of traditional congestion-control architecture are analyzed. And by research on traffic-control model and FPGA features the internal router traffic management is solved.Firstly, the push-type and pull-type traffic-control model are introduced, the features of FPGA are outlined, and especially the basic structure and major design process are researched. According to system requirements, the system architecture, overall design and subsystem design are presented. Key technologies:Hierarchical traffic management, SrTCM, trTCM, MEF10.1, WRED and other common traffic management algorithms are introduced.And then the further and detailed analysis is made on algorithm and implementation of traffic policing subsystem, data flow and algorithm of congestion avoidance subsystem, authorized distribution and queue management of congestion management subsystem, and data flow and implementation of traffic shaping subsystem.Finally the new traffic-control scheme of routers based on FPGA is simulated and verified. The experiment test results show that the scheme provided in this thesis reasonably solve the problems about the internal congestion of routers and end-to-end traffic control, which allows the router of forward packets at wire speed, and improves the integral performance of routers.
Keywords/Search Tags:Router, FPGA, Hierarchical Traffic Management, Congestion Management
PDF Full Text Request
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