A Design Method Of POS Interface Based On ASIC+FPGA In Core Router

This article introduces a hardware design method of 155Mbps POS interface in core router which is based on ASIC+FPGA -- two pieces of PMC PM5351 chip 155Mbit/s×4 and Altera Stratix FPGA. The POS has the ability of 8×155Mbit/s O/E, reseting of clock and data ,framer corresponding ,connecting the network processing card by bus SPI3/ SPI4.2 in PPP, reporting the work to network processing card by cpu port.Simultaneously carries on the extraction and operation in the movement, maintenance and performance surveillance on physical layer& data link layer . Contains optical receiving&transmitting module ,clock and data reseting module ,POS framer module, EPLD,FPGA and so on.The design of FPGA is the key section ,its chief function is that tranmitting the datas between Framer in interface and network processsing card and receiving PPP framer from interfaces to network processing card and then bringing the framer coming from network processing card to155Mbit/s POS Framer .FIFOs in interfaces of chip PM5351 are limited so it is very easy to discard data packets,as to operate queue and transmit data ,FPGA also can supply big room by RAM which has the effect of storage.As a whole ,the design achieved the anticipation .