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Design And Implementation Of High-frame-rate And High-resolution-ratio CMOS Camera

Posted on:2014-02-14Degree:MasterType:Thesis
Country:ChinaCandidate:P C CongFull Text:PDF
GTID:2248330395499646Subject:Measuring and Testing Technology and Instruments
Abstract/Summary:PDF Full Text Request
High-frame-rate and high-resolution-ratio image acquisition is wide-range in applications such as industrial programs, scientific researchs and military affairs. The research of high speed camera in China lags behind other countries. It’s very important to carry out the research work of High-frame-rate and high-resolution-ratio camera.This paper presents a design scheme of high-speed CMOS image acquisition camera based on FPGA, DDR2and USB3.0. The system design is finished based on the study of the CMOS image sensor, storage of mass data and high speed thansmission of mass data. This high-speed camera is composed by four modules. They are image acquisition module, image storage module, data transmission module and image display module. Lower position machine system is composed by the previous three modules and on position machine system is composed by image display module.Using modular design solution, this system chooses Cyclone Ⅲ FPGA as main controller, cmos image sensor as optical-electrical converter, DDR2array as storage medium and USB3.0interface as transmission path. This paper discribes system design philosophy in detial and introduces PCB design methods.Software design includes FPGA coding and C++coding. FPGA software design is based on Verilog HDL, this paper expounds sequential logic of each hardware modules and handshake signals between modules. Instantiation of two dual-port RAM in FPGA and ping-pong operation between them give a solution for receiving high-speed serial data generated by CMV4000sensor. Slave FIFO model fulfils the control task of USB3.0channel. Using MFC, Cypress API, multi-thread and memory remapping, on position machine system software Implements functions of image display and image storage etc.High-speed camera involves complicated hardware and software, this paper introduces the common error detection and debug method.The testing results show that the system can work at180frame/s at image resolution of2048*2048and360frame/s at reduced image resolution of2048*1024. Therefore the camera has great practical value.
Keywords/Search Tags:Image acquisio n, CMOS image sensor, DDR2array, USB3.0, FPGA
PDF Full Text Request
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