Multi-channel Broadband Signal Collection And Processing System Design And Implementation

In radar system, especially in the background of application of Phased array radar or radar imaging, A great quantity of data need to be collected for the real-timing processing or processing and analysis after storage. In this paper we discuss the collection of multi-channel high performance data, signal processing and storage system design which are the focus research at home and abroad.Firstly,we analyse the theories about the integrity of signal and power source;On the basis of these,we introduce some commonly used methods about inhibiting signal reflection of transmission line, cancelling crosstalk, minimizing noise of power synchronous switch, which are applied in the PCB design.PCB design includes the layout of circuit; arrangement of wire; laminated design, impedance control, and power supply division,etc.Secondly,we analyse the techniques of bandpass sampling within the application of data collection,then through the simulation of Matlab,introduce a method about channel correction which is based on correction filter estimated,and verify it has high performance.Subsequently,we put forward the overall function and technical requirements in multi-channel and high speed data acquisition system,determine the core chips of the hardware system;and discuss feasibility of this system design from the angles of power supply network design,ADC circuit design,data transmission interface design of FPGA and DSP,and FPGA pins allocation; finish the scheme design, PCB design and PCB simulation test.Finally,complete performance test of the whole power network on the PCB board,verify the correction of the power order of core chips,debugging the ADC configuration interface and data output interface,test the AD conversion performance and obtain the effective bites of ADC.Debugging the DDR3controller interface and through the reading and writing tests of the DDR3controller,verify the correction of results,the same method,debugging FPGA and ARM communication interface and verify correction of results.