The Design And Implementation Of Digital Array Radar Dbf Processor

With the development of the microwave integrated circuit, large scale and high speed integrated circuit and optical fiber transmission technique, the Digital Beamforming(DBF) technique will be widely used for Digital Array Radar(DAR) which process data in all-digital way. As the core component of DAR, the development of high-performance DBF processor becomes a hot topic in radar field all over the world.According to the requirement of DAR system, a DBF processor is designed and developed based on the architecture of two FPGAs and one PowerPC in the paper. The main work in this paper includes the design, simulation and validation of DBF processor based on FPGA. Besides, all functions of DBF processor are verified under the specialized DBF testing simulator. It has the characteristic as follows:1. It is remarkable for its powerfull data-transfer capacity by12channels of3.125Gbps optical fiber transmission interfaces so that it could meet the requirement of tremendous data throughtout in DBF radar system.2. It has outstanding High-speed data storage and parallel processing capability.The processor adopted Xilinx XC5VSX330T FPGA with a lot of logic, block RAM and DSP resources, which is suitable to realize12receiving and4transmitting DBF processing with100sub-array elements.3. One lOGbps Serial RapidIO interface is adopted to realize fast and reliable date transmission between PowerPC and FPGAs, which is fit for real-time update of the DBF weights coefficients.