Research On Address Mapping And Instruction Decoding In Co-design X86System Emulation

With the rapid development of microelectronics technology, the processors with newarchitectures are emerging continuously and the scarcity of software application resources ishighlighting seriously. Having the software application of X86which dominated the CPU marketposition ported to the new processors is an effective way to achieve the universal application ofthe new processors. The X86system emulation based on hardware software co-design caneffectively solve the problem of―code migration‖and architecture compatibility by introducingappropriate hardware part, making the software parts worked together with the hardware parts toeffectively improve the performance of X86system emulation and having become an importantsupport technology of the new processor applications.This paper analyzed the key factors which restricting the performance of X86emulation andhad a reasonable hardware software division for emulation function module, presented a X86system emulation model based on hardware software co-design and constructed the X86systememulation Co-AB on the host machine of OpenRISC, having testing and verification of theCo-AB on the OpenRISC SoPC based on FPGA. Design and realization of the HardTLB andHardTLB accessing instructions, making the SoftMMU and HardTLB worked cooperatively byembedding assembly instruction, accelerating the performance of address translation during inmemory access; Proposes an emulation mechanism of pipelined instruction decoding, design andrealization of the pipelined instruction decoding unit, overcome the problem of serial decodingmechanism lower performance and reduced the time of instruction decoding.Verification and experiments showed that the Co-design VMMU and pipelined instructiondecoding unit could correctly complete the mapping of address and instructions decoding. Theco-designed VMMU unit improved the performance of memory access by36.7%compared tothe traditional software implementation. The pipelined decoding mechanism reduced theinstruction decoding cycle by41.8%compared to the serial decoding mechanism.