Design And Implementation Of A CPCI Interface Data Decoding System Based On FPGA

CPCI interface data decoding system based on FPGA is designed as a part of the communication receiver system. It is mainly in order to achieve the signal data decoding, processing, collection, storage and management. With the core foundation including CPCI bus technology and the industry mainstream field programmable gate array (FPGA), the data decoding system can provide good stability and data decoding capabilities to the communication receiver system.The thesis presents a design scheme in which DALLAS Company’s DS3131is used as the bridge interface chip and Spartan6Series FPGA as the core of the CPCI bus data acquisition system. A data acquisition card is designed for the system running on a CPCI bus industrial computer, and the application software helps a user to complete data storage with a remote data server as the destination.For hardware, this thesis is based on the present mainstream Xilinx low-power FPGA Spartan6series, to meet the cost control requirement as well as the high-performance requirements to the core chip. The bit synchronization (Boss) HDLC protocol controller DS3131introduced by Dallas Semiconductor is used as the Local Bus and CPCI interface. The data collection and application software can control the on-board devices in real time. The Altium Designer circuit design software is used to complete the hardware design based on the bottom-up design manner.For software design, the thesis makes use of a driver development software Windriver to generate the driver framework and develops the user application software using C++programming language. The software mainly completes the CPCI interrupt response, off-site data storage and SQL database management.Works completed include the hardware circuit board development, welding and debugging. The actual use of the driver and application software is tested. After the functional and timing simulation, the FPGA program developed by hardware description language is put into practice by actually writing into the device through the JTAG download cable. Together with the remote data server, the preliminary test of the overall system is completed.