| The computer industry is currently dominated by the single processor architecture. The fixed bandwidth between processor and memory is now such a limiting factor that machines are best described by their bus speed. Also, single processor machines have a fixed performance limit that cannot be surpassed.; The Computational RAM (C{dollar}cdot{dollar}RAM) project attempts to solve these problems by placing thousands of Processing Elements inside an existing computer part with lots of internal bandwidth: the main memory. A prototype C{dollar}cdot{dollar}RAM was designed at IBM Microelectronics in Burlington Vermont by adding 1024 SIMD Processing Elements (PEs) to a platform 16 Mbit Dynamic RAM. They were installed on a pitch of 8 sense amplifiers outside the predesigned array blocks using static CMOS logic and a 0.8 {dollar}mu{dollar}m process. This change increased the chip's area by 14% and simulations showed a power consumption increase of 11%.; C{dollar}cdot{dollar}RAM is a JEDEC-compatible Dynamic RAM chip with an additional parallel processing mode. In addition to regular memory I/O operations, it can be used to perform vector computations, database operations, and real-time image processing. A single chip can perform 462 million 32-bit additions per second, and sort M data elements with an O(M) algorithm. Discrete Cosine Transforms and motion estimation, the two heaviest components of MPEG-2 video compression, can be performed for more than 30 frames per second. The DRAM's fast page mode is used to increase memory bandwidth to the PEs, and makes computations three times faster. |
