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FPGA-based High-performanee Logic Of Building A Database Of Parameter Libraty

Posted on:2013-04-10Degree:MasterType:Thesis
Country:ChinaCandidate:F ShiFull Text:PDF
GTID:2248330395456183Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the fast developing of design standards and the manufacturing processtechnology about the Ultra-Large-Scale-Integrated-circuits, the degree of automationof the design tools and flow become more automated and intelligent, while the librarybuilding technology of this flow plays a fundamental role. When users change parts ofthe standard cells or PADs of the library, or according to the actual application, theyhave to extend the library temperature range from industry degree to full degree, sothey need to change or rebuild the logic parameter library. Today, the ideas of ICdesign, with the design reuse is more advocated, the building of Intellectual Propertyhas close relation with the technology of building of library.In this paper, the specific work content is based on of a6million project abouthigh performance FPGA. Finally, we established a set of standard cell logic parameterlibrary which is very accurate. At the same time we established a FPGA softwaresystem of building library; Moreover, we solve some technical problems and some ofthe key technologies were improved. We focus on the method for the excitationwaveform generation of the combinational logic circuit units, we generate simulationincentive automatically by a simple way in this project. We analysis of the extractionof the capacitance parameter and power modeling detailed, and show two model ofequivalent capacitance. In this paper, we found some difficult problems, such assampling point offsets and fast approaching static operating point, we solve theseproblems successfully. At last, we optimize and verify library and software system ofbuilding library. It proved that the library and the software system of building librarywe build in this paper, is not only effective but also accurate.
Keywords/Search Tags:structured FPGA, library building, parameter extraction, stimulus generation, equivalent capacitance
PDF Full Text Request
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