Research And Design Of High Speed Adaptive Filter Based On FPGA

The study of the filtering performance of the adaptive algorithm has beena hot topic of research in the field of digital communications branch.Scholars focused on the adaptive algorithm in order to improve the filteringcapabilities and indicators to enhance the adaptive algorithm, but therelatively small study of high-speed implementation of the physical hardwareaspects, which are mainly for the LMS algorithm. The structure of LMSalgorithm is simple, but with the shortcomings of the poor characteristics.With the advent of the era of3G/4G communications systems, the rate andother numerical characteristics of adaptive signal processing techniques havebecome increasingly demanding. Therefore, research high-speed adaptivealgorithm which has more excellent characteristics than the LMS algorithmhas great practical significance.In this thesis, the main model for adaptive signal processing is noisecancellation, and adopted FPGA which is more efficient than DSP as theanalysis platform. Algorithm analysis and the implementation section, Firstanalysis the algorithm performance and computational complexity of thetraditional LMS algorithm and RLS algorithm; next，analysis the adaptivegradient lattice filtering algorithm, and compare the performance and thetechnical complexity to the LMS algorithm and RLS algorithm; Then analyzeand improve the architecture of the LMS algorithm and lattice algorithmwhich are suitable for high-speed hardware implementation，take advantageof FPGA development tools for hardware implementation.The improvements proposed a delay leading transfer and retimingoptimization strategy for adaptive gradient lattice filter structure, which has ashorter critical path, and conducive to high-speed FPGA implementation.Then use the DSP Builder to implement these algorithms. Then in the sectionof application, describes the example application of the radar receiver of an electronic support measures system which used high-speed adaptive filteringsystem.