The Design And Implementation Of Adaptive Filter Algorithms Based On Fpga

In this work, for the structure and characteristics of the adaptive filter, analysis and design in the common structural and applicable environment, to find a suitable filter structure and optimized, makes it ideal for FPGA implementation.The correction for the theoretical analysis and feasibility for the design are confirmed experimentally. The mainly content of this work includes:In the non-stationary environment, adaptive lattice filter can not effectively track the changes of input signal, but adaptive transverse filter can make up this limitation. Adaptive transverse filter can adjust the weight coefficients by the error between output signal and the desired signal automatically, then tracking the input signal in real-time, so as to achieve a better filtering effect. The method of combining the lattice type filter structure with transverse filter structure, not only solve the shortcomings that the signal can not be tracked in real time in lattice filter, but also improve the convergence rate of weights in transversal filter. This solution lowered the complexity of system design.In the lattice filter, the characteristics of adaptive lattice structures that the sessions of the lattice structure reach a certain extent, the reflection coefficient approaches zero. For this feature, using a delay structure to replace the rear sections of the lattice structure can achieve the same effect, and saving a lot of resources.In the lattice filter structure, the input of after section relative to the previous input is closer to the ideal output, If use the same step size, then the after section step is so large that may lead to divergence. This article use different steps to update the reflection coefficient, and choice2-L (L is an integer) for the step factor, by shifting to achieve, not only can improve processing speed, but also conserve resources.Based on the characteristics of the two filters mentioned above, this design realized a filter on FPGA-based hardware platform and ISE9.2i development platform with Verilog language.The overall design and the concrete realization of the modules is done in this thesis. This paper realizes the functional simulation of the algorithm based on ModelSim SE6.5, and the results show that the algorithm meets the requirements of this design.