| With modern advances in technology and manufacturing industry, non-destructive testing (NDT) technology has been widely used in many importantindustrial sectors. Non-destructive testing technology will help to improve themanufacturing process, reduce manufacturing costs, improve product reliability, andto ensure the safe operation of critical equipment. NDT application level basicallyreflects the development of an industry, and even the development of a country.Many methods are applied in NDT application. These methods includeultrasound, radiation, eddy current, magnetic practical, etc. And ultrasound method isthe most widely used one. The effect of ultrasonic inspection depends largely on theperformance of ultrasonic flaw-detection instrument. The core algorithm of most ofthe ultrasonic flaw detector is implemented by the FPGA. Some of the key modulesof the ultrasonic phased array flaw detector in the FPGA design have been studied inthis paper, and the design implementation and verification on hardware are alsocovered.At first, the hardware architecture of phased array flaw detector and the FPGAfunction requirement are introduced. The FPGA function is divided into severalblocks and this paper will focus on the ADC interface, the display subsystem, theprocessor interface, as well as high-order and big-width FIR design.The SelectIOTMresource of Xilinx FPGA is used to connect the high-speedserial data ports of ADC. The ADC interface supports700Mbps data transfer rate byutilizing ISERDES component and dedicated clock buffer of IO tile. A dynamicdelay fine-tune solution is created to combat the clock and data jitters caused byharsh field environment.To ensure real-time display of the ultrasonic echo wave and envelope, theecho/envelope plotting algorithm and menus/wave display control mechanism arediscussed in details. A TFT LCD module is used as display device, and the menudisplay area and A-scan display area are stored in external memories respectively.FPGA internal RAMs are used for the A scan envelope calculation.There are various types of data exchange between the processor and FPGA. Foreasy deriving processor interface in other FPGA function modules, the transactionsbetween FPGA and processor are abstracted to three categories. Each category isimplemented with generic parameters, and can be invoked in other design moduleswith minimum modifications. Echo signal processing FIR needs high order transfer function and large bit-width. In this paper, a time-division multiplexing semi-parallel FIR structure isdescribed, which supports non-symmetric64coefficients and symmetric127coefficients FIR. Taking advantage of the achievable high operation frequency ofFPGA, the FIR design saved as much as possible multiplier resources whileminimized the FIR latency. |
