Research On Phased Array Ultrasonic Imaging Algorithms And System Design

Ultrasonic phased array technology can control flexibly the spatial and temporal characteristicsof ultrasonic beam. It can obtain visual image of detecting result and improve detecting sensitivity,resolution and SNR, so that it has recently been highly recognized in International NDT research field.Based on research on phased array ultrasonic imaging algorithms, this paper aims to develop a32-channel phased array ultrasonic imaging system, and implement and verify algorithms related toultrasonic phased array technology on this hardware platform.The main works are shown as follows:1.In-depth studied the principle and imaging algorithms of ultrasonic phased array technology,and discussed the relationship between delay precision and system resolution; Besides, abeamforming algorithm based on quadrature envelope detector technology is used in this paper,.through analysis and verification, we know that this algorithm has higher spatial resolution and noiseimmunity, lower sampling rate and storage requirements than the traditional algorithm.2. A virtual array ultrasonic imaging method is proposed. This method excites one single arrayelement at once, avoids the requirements of high-precision delay, and greatly reduces the difficulty ofimplementation. A simplified receiver model is presented, which can reduce the implementationcomplexity. Besides, this method has higher spatial resolution than the phased array fan-shapedscanning imaging method.3. A hardware design scheme of32-channel phased array ultrasonic imaging system is proposed.Based on modularization design concept, the paper completed the designs of ultrasonic emissioncircuit, High voltage generation/isolation circuit,32-channel receiver, FPGA and embedded processorsystem. ADI’s8-channel AFE chip AD9273is used to improve the integration of receiving system;Xilinx’s Spartan6family FPGA is used to improve real-time peocessing; ARM11microprocessor isused to improve the post-processing and display resolution.4. Completed schematic diagram design, PCB design and debugging of each subsystem, and theycan work properly; Completed the interface debugging between32-channel receiving system andFPGA subsystem; Completed the interrupt and DMA debugging between FPGA and ARM11microprocessor; Completed hardware description language programming of virtual array ultrasonicimaging method, and verified in FPGA.