HW/SW Co-Verification Platform Research For MPSOC

In today's market of IC product, the time to market has gained more importance than the performance,power and cost, and become the upmost criterion by which the product's success is weighed. In the design flow of an IC product, 70% of the total design time is spent on the system verification. So designers have to shrink the verification time of the product, in order to shorten the time to market. With the constant development of verification technique and the fact that SOC has become prominent in the IC design field, hardware/software co-verification is getting more and more focus of the IC designers.According to this situation, this paper brings forward a new hardware/software co-verification method for multi-processor SOC. This method is based on the traditional HW/SW co-verification technique, and add a Verilog HDL to SystemC translator. The translator eliminate the difference between the software and hardware system, so as to make it possible to verify the software and hardware system within a single engine, and avoid the inter process communication brought in by the traditional HW/SW co-verification.This new HW/SW co-verification method can improve the efficiency of system verification, remarkably reduce the time spent on verification, and can therefore shorten the product's time to market.The new HW/SW co-verification platform has been through tests after it is built. The results of the tests show that this HW/SW co-verification platform can appropriately perform the verification of the multi-processor SOC, and demonstrate significant improvement in system verification time compared to the traditional HW/SW co-verification platform.