Research On Evolutionary Design Of Circuits Based On Memetic Algorithm

Evolvable hardware（EHW） technology is a new circuits design approach with the rapiddevelopment of Electronic Engineering and Biology.EHW can also provide a new method indesign of self-repairing and fault-tolerance system, With the ability of exploring the wholesolution space,the EHW technique could find some novel hardware structures which possessthe features of low-power,fault-tolerance and area-efficency.The EHW needs rarely domainknowledge,which could reduce the design cost.so EHW is used in many fields, especially inaerospace and military equipmentThe purpose of this dissertation is to research rapid convergence algorithm for circuitevolution design based on EHW,The main research works of this dissertation can besummarized as follows:The principles and realization methods of EHW have been systematicallyintroduced.The Evolvable algorithms and Programmable Logic Device （PLD） which arethe key technology of EHW are analysed deeply.The realization principle,working processand realization methods of Memetic algorithm are researched in this paper.To solve problems of traditional evolution algorithm, such as slowness evolution speedand premature convergence, this paper presented an memetic algorithm（MA） that combinesthe local search method with genetic algorithm for combinational logic circuit design basedon CGP. The fitness function used in the experiments is sequential,that is,divided in twoparts.The first part of the fitness function f₁evaluates the circuit functionality,while the secondpart f₂deals with the circuit complexity.The experiments consist in applying the algorithms inthe design of two arithmetic circuits:the one-bit full adder and the one-bit full subtractor.Experimental results shows that It is efficient and can improve the global convergence abilityand enhance the rate of convergence.We also present a scalability analysis through compareexperimental data.One of the main difficulties in using EHW to solve real-world problems isscalability,which limits the size of the circuit that may be evolved.This paper outlines a newtype of decomposition strategy for EHW,the“circuit mapping”（CM）, which allows theevolution of large circuits. and a algorithm which combines CM with memetic algorithm（MA）is proposed. It divides the system into some simple ones regularly until the function isachieved.This decomposition process consequently dispense with human interference.Themethod has been tested with multipliers and Parity check circuit. In order to achieve statistically relevant results,each analyzed logic circuit has been evolved30times. Theexperimental results show that it greatly enhances the efficiency and hit effort of evolvingdigital logic circuits.