Research And Implement Of Packet Transport Network Store-and-Forward And Scheduling Key Technology

With the rapid progress of network and ever-increasing traffic over Internet, Store-and-Forward and scheduling are facing the pressure of enhancing forward rate, expanding throughput, offering quality of service and so on. In the network, increasing exchange amount of data makes Store-and-Forward technology is becoming the bottleneck of the network. Meanwhile, the increased number of interconnected IP core and the requirement of affording different services according to different priority levels of communication between different IP cores make people present a higher request to Store-and-Forward and scheduling technology on Network on Chip.In this paper, on the basis of analyzing kinds of Store-and-Forward and scheduling technologies, we deeply learned this technology from two aspects:Packet Transport Network (PTN) and Network on Chip (NoC).First of all, according to the demand of large storage capacity, fast forward speed and providing various traffics of PTN, we designed a linked list queue management circuit based on output queue. Every output port had multiple queues possessing different priority levels, which could satisfy different services of quality according to different traffics. At the same time, occupied resource of every queue could be refreshed in real time according to stored packet description numbers, immensely improving the utilization rate of storage. Circuit synthesis was done by using Design Compile of Synopsys, Inc. The result showed that the circuit could operate at195MHz, the area of which was at around29,000logic gates (not including storage area). For the sake of realizing comparison results automatically, we build a queue management unit reference model (QMURM), and use it in the function simulation of queue management circuit. To a large extent, we improve function coverage rate and simulation efficiency.Secondly, according to the demand of low latency and high clock frequency of virtual channel router, we present a new kind of low latency virtual router implementation. Virtual channel (VC) allocation and switch allocation employed speculative allocation mechanism and fast allocation mechanism, which could propose VC request and switch request simultaneously, and respond to them as soon as received them according to the calculation result of previous clock cycle. Meanwhile, this paper learned and implemented look-ahead mechanism. Those mechanisms ensured that virtual channel router could complete store-and-forward operation in one clock cycle. Compared with the traditional pipelined router, forward latency was reduced immensely. On the basis of optimizing architecture, we analyzed and optimized the critical path as well, and made the router has a higher clock frequency. The chip was implemented in SMIC’s130um Mixed-signal/RF1.2V/3.3V process. We test the chip operated at300MHz clock frequency and analyze the testing result. Last but not least, for improving functional simulation’s efficiency and shorting simulation time, this paper designed a hierarchical reusable verification platform. It could generate kinds of random, oriented, false test case, meanwhile provided code and functional coverage rate. This platform employed an effective algorithm generating test case and modeling port rate of gigabit router. Compared with traditional verification technique, this platform could improve verification efficiency, short design cycle and process completely verification to tested circuit.