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USB2.0Host Controller IP System Verification Based On SW/HW Co-simulation

Posted on:2013-11-18Degree:MasterType:Thesis
Country:ChinaCandidate:J T LiFull Text:PDF
GTID:2248330377452355Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
With the development of IC design and manufacturing technology, thecomplexity and scale of the integrated circuit have been on fast-growing. The growthof the complexity and scale leads to the increasing requirement for the functionalperformance to be verified, which, with the interaction between different modules,will cause more difficulties in the process of verification. In the development processof SOC, verification is the most key and time-consuming module. It is of greatimportance to select a quick dependable way to verify the design and functionalperformance of IP modules integrated on SOC.USB bus has become the main bus standard due to its excellent performance,which is widely applied in the field of computers, telecommunications and consumerelectronics. Nowadays, USB is a commonly-used interface in the design of domesticdigital television and USB master controller or USB OTG IP core is integrated onmost ASIC chips for digital video processing.In the research, the system performance of the USB2.0master controller IP coreon digital television SOC is verified, and USB2.0master controller is integrated ondigital television SOC. The verification of USB2.0master controller is implementedin the way of hardware-software co-simulation. In this project,AHB bus is as theframework of digital television SOC. Based on this,an AHB host TLM modeldesigned by System C is introduced in the CPU module of the verification platform,which convert the execution of upper C language to AHB bus time sequence tocontrol the master controller to be verified. The experiment proves that the executionspeed of the simulation platform integrated with the CPU model is11times largerthan the platform with RTL CPU model, and4times larger than the platform with ISS.USB interface of the USB2.0master controller is connected with the peripheralverification IP from third parties to detect the master controller’s executionperformance of the protocol. The introduction of VIP simplifies the establishment of the verification platform, accelerates the process of verification and improves thecredibility of the verification result.The hardware-software co-simulation platform designed in the process ofverification for the USB2.0master controller IP functional performance isemphatically introduced in the paper, and the related protocols with the IP andsupported function for the master controller are also analyzed. According to theanalysis, testcases is designed for different function points, which fulfills thefunctional performance verification for the master controller. At the end, thesimulation result is analyzed in detail.
Keywords/Search Tags:SW/HW Cosim Verification, CPU Model, USB2.0MasterController, SOC
PDF Full Text Request
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