Rtl Level Systems Interconnect And Circuit Of Software Automation Test Method Research

Because SoC is more complicate, only when all the functions of the IC are fully verified before tape-out, the IC can be successful. So the technology of the IC verification is more and more important.For IP verification, all the EDA tool venders(such as Cadence, Synopsys) have developed very ripe verification methodologies. Using these methodologies, all the IPs can be fully verified. But for a complete SoC, in addition to the fully verified IPs, there some wire interconnections and system circuit. But for the wire interconnections and system circuit, no ripe verification methodology has been developed. The efficiency of the common verification method for these circuits is very low. The low efficiency largely impacts the total verification quality. Some ICs can be found bugs after tape-out. The IC is tape out again after these bugs are fixed. So the time to market will be delayed. These iterations largely raises the IC cost and may lead the company to lost the potential market.In this thesis, to fully verified the wire interconnections and system circuits, new verification methodologies are developed. And to get the high verification efficiency, the idea of the auto-test is implemented. The main results are as follows:1.The traditional verification methods of the wire interconnections and system circuits are investigated in detail.2.The characteristics of the wire interconnections and system circuits are discussed. And because of the same characteristics of these circuits, a common method can be used to describe the behaviors of these circuits.3.New verification methodologies for the wire interconnections and system circuits are developed.4.The Feasibility of the auto-verify is investigated5.The auto test scripts using Python language are implemented. These scripts can guarantee the verification efficiency and completeness.