Broadband Radar Reconnaissance Receiver Digital Control Design And Fpga Implementation

The reconnaissance processor for radar signal is a key system in the field of radar countermeasure. It’s the base of Electronic Counter Measures (ESM) system and Radar Warning Receiver (RWR). Aimed at the characteristic that wideband digital reconnaissance need deal with multi-signal at the same time and based on the architecture of digital reconnaissance formed by multi-level channelization and DSP arrays, this dissertation designs a scheme of digital central control on the basis of buffer management and computing resource scheduling. The main content includes four areas as follows:1. In environment of modern radar electronic warfare, the trend of reconnaissance receiver is researched. After introducing of digital channelized receiver, a system architecture of digital reconnaissance receiver based on three-level channelization is given. On the basis of analyzing the signal processing ability and pulse density of DSP, the signal processing scheme based on DSP arrays is presented. The basic function of digital central control of reconnaissance receiver is illustrated, then the key technology and implementation methods of the digital central control are discussed.2. Based on the first order phase difference characteristics of radar signal and aimed at the fact that some radar signal is too long to be processed totally, the feasibility of radar signal truncation is discussed, then a simple and practical implementation method is given. Based on structure of three-level channelization and the signal processing scheme of DSP arrays, different buffer schemes are compared and a data buffer structure which has good throughput is presented. Then its control method is given.3. The structure of parallel processing system is researched. The key elements of parallel system such as topological structure of DSP arrays, internetwork and parallel task sharing methods are analyzed, and then their correlations are discussed. Based on introducing the characteristics of data interconnection network, the structure and control strategy of data interconnection network is given after discussing the dynamic interconnection network. 4. To demonstrate the practicability of digital central control design, a hardware and software combine-test system is designed and testified.