Font Size: a A A

Based On 20 V Nldmos Structure Design Of Esd Protection Devices

Posted on:2013-04-30Degree:MasterType:Thesis
Country:ChinaCandidate:L J LinFull Text:PDF
GTID:2248330374985778Subject:Microelectronics and solid-state electronics
Abstract/Summary:PDF Full Text Request
As the semiconductor IC technologies advances into the very-deep-sub-micron regime, ICs become increasingly susceptible to ESD(electrostatic discharge) damages. Statistics indicated that up to30%of all IC failure might be attributed to ESD, which costs the semiconductor industry billions of U.S. dollars annually. Such ESD-induced failures are either catastrophic or latent in nature, with the former causes immediate IC malfunction and the latter leads to future failure and lifetime problem. Accordingly, appropriate ESD protection are developed to protect IC parts against ESD damages.The content of this paper is to study and optimize the working performance of an20V NLDMOS(N channel Lateral Double-diffusion MOS) under ESD condition. First, based on the ESD protection theory, the article introduced the four common types of ESD protection devices, including diode, BJT, MOS and SCR(Silicon Controlled Rectifier). After, some difficulties to design the high-voltage devices during ESD events were explained. Then, the simulation software Sentaurus was used to study NLDMOS in ESD protection. Based on the TLP(Transmission Line Pulse) test, the reasons of soft leakage were studied, including electricly field induced and thermally induced, and then the solution was proposed, that is increasing the length of the LOCOS(Local Oxidation of Silicon) uper the drift region. Some parameters of the device were optimized by simulation respectively, including the channel length, the length of field plate, the distance between the drain contact and LOCOS and the distance between the injection of source and bulk. Based on the NLDMOS, an SCR was designed, and the working characteristic of the SCR was analyzed and optimized by simulation. Then, some of the layout optimization technique which were used in the test structures were listed, the optimization of the active region and the contacts of the drain were contained.Those optimized devices were verified in a0.35μm BCD process. The test result shows these optimized devices have already solved the soft leakage problem and the ESD robustness of the device is improved.
Keywords/Search Tags:ESD, High-Vlotage Device, LDMOS, SCR
PDF Full Text Request
Related items