High-voltage Soi Ldmos Breakdown Mechanism Analysis And Device Fabrication

SOI, namely Silicon On Insulator, device and IC have many advantages: low leak current, weak parasitic capacitance, low power loss, radiation hardness, and high integreted level. High voltage SOI SPIC is a new field of Power IC. High voltage SOI devices investigated in this thesis are key devices for high voltage SOI SPIC. It is one of trial projects of defensively science laboratory. High voltage SOI lateral MOS devices studied in this paper are early application work for SOI SPIC.The breakdown mechanism of SOI LDMOS with located charge trenches was analyzed in this thesis. The interface charge model for the breakdown voltage was proposed. Charge Qs was located near the interface of silicon and oxide. With more charge, the field of buried oxide was improved up to the critical breakdown field basis on entirely continuity of electric displacement vector, and then the vertical breakdown voltage was raised. The comparisons between analytical and simulative results proved its availability of this model to interpret the vertical blocking mechanism. The distributions of interface charge in the bottom of trenches and electric field in insulation layer were studied for the novel structure. The influences of insulation layer thickness and trench width on breakdown voltage were analyzed and compared with analytical results. The influences of the technics error on reverse characteristic were also investigated.An entirely new structure of high voltage SOI LDMOS with located charge trenches in vertical and a lateral trench with a shape of U was studied. With lots of analysis on this new compound structure, the breakdown voltage was raised 30% and size was reduced to 60% of the common SOI LDMOS.A feasible way to produce SOI material with located charge trenches was presented. The process programs of SOI LDMOS were finally given.