High Speed Low Phase Noise Pll Research And Design

The Phase-locked loop introduced by De Bekkescuze in1932has been a wide range of applications and development, which can be found in every corner of the electronic products and becomes a core component of electronic systems in modern electronic technology. With the development of modern communication, radar technology, and electronic warfare technology, its performance requirements are also getting higher. And the indicators required by different applications are different, which lock time and phase noise has always been widespread concerned, because the lock time directly affects the data transfer rate of the communication system, phase noise has a tendency to increase bit error rates and degrade the signal to noise of the system. In addition, the increasingly narrow communication bandwidth needs a higher frequency resolution. It is difficult to achieve the targets simultaneously by a simple PLL due to the mutual checks of the indicators.Firstly, the dissertation briefly introduces the development and application of the phase locked loop technology. Then the operating principle of the important components in the phase-locked loop system is analyzed to show the problems in practice. The impact of the noise from loop components on the PLL phase noise is presented. The results from simulation by behavioral models prove the system can achieve minimum phase noise by optimizing the loop filter bandwidth. Studying the dynamic performance of PLL in the process of lock-in by simulating the linear models, which are based on the time-varying reference frequency or time-varying frequency divider. The analysis of the dynamic performance of the PLL with a Phase Frequency Detector in the process of pull-in is based on the physical models and nonlinear methods. The simulation results prove that presetting voltage can greatly improve the settling time of PLL. SIMETRIX as a simulation software can carry out mixed-signal simulation of analog and digital circuits, the behavioral model simulation greatly reduces the simulation time. The results of simulation show that the design project is reasonable.Finally, on the basis of the theoretical analysis, a high-speed phase locked loop with low noise is designed, which has an output frequency range of1200MHz-2400MHz. Experimental test show that phase noise of the phase-locked loop is below-90dBc/Hz at10kHz offset, the hopping time is about33us, the frequency resolution is10Hz, fractional spurious can also be a good inhibition by Sigma-Delta modulator technology. All these indicators meet the design requirements well, but the reference spurs of system are to be further improved.