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Research Of Fast-locking In C-band PLL Frequency Synthesizers

Posted on:2014-08-11Degree:MasterType:Thesis
Country:ChinaCandidate:Y W NingFull Text:PDF
GTID:2268330401965380Subject:Electromagnetic field and microwave technology
Abstract/Summary:PDF Full Text Request
Frequency synthesis technology is the very important part of in the modernelectronic systems, Because phase-locked frequency synthesis technique can be a goodchoice for the frequency of signal, restrain stray component, and don’t have a lot use ofuse filters to filter our unwanted components. So it is very beneficial for modular,integration and miniaturization, so it is widely used in various kinds of electronicdevices and systems.This thesis briefly discusses the working principle, the basic composition,mathematical mode and the loop steady-state tracking performance of phase-lockedfrequency synthesis technique, and discusses the methods to minimize the lock time ofthe phase-locked loop. On this basis, use a series of measures, including:(1) usingdecimal frequency division to improve the phase frequency in order to increase the loopbandwidth;(2) using FPGA to realize high speed parallel control;(3) with high speed,high precision and parallel interface D/A converter to the VCO tuning voltage presetreduce the frequency difference of phase-locked synthesis;(4) Calibration of the VCOtuning voltage by A/D converter, improve the accuracy of preset voltage. Design, makeand debug a C-band phase-locked frequency synthesis, which is based on HMC704phase-detector chip and HMC507VCO chip, using passive of third order loop filterstructure. In the voltage-presetting module, use a high speed D/A converter which hascurrent outputting and use a high speed, low noise operational amplifier THS4031converting the output current to the high precision of the DC voltage, again through thecombiner constituted by THS4031, preset precisely the VCO tuning voltage. Though theour test, this phase-locked frequency synthesizer can generate6.65GHz~7.65GHzfrequency range, the frequency step is1MHz, the fractional spurs suppression is betterthan-65dBc. Phase noise is better than-90dBC/Hz@1KHz,-95dBc/Hz@10KHz,-110dBc/Hz@1MHz. The hopping time is less than20μs when the hopping frequencydifference is1GHz frequency compared to not using preset voltage frequency which has262μs hopping time, frequency hopping time reduced by92%.The research of decreasing locking time of broadband phase-locked frequency synthesizer in this thesis, has very important significance and application prospect.
Keywords/Search Tags:Voltage Presetting, PLL, Frequency Agility
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